Руководство по attiny2313

Features

Utilizes the AVR® RISC Architecture

AVR – High-performance and Low-power RISC Architecture

120 Powerful Instructions – Most Single Clock Cycle Execution

32 x 8 General Purpose Working Registers

Fully Static Operation

Up to 20 MIPS Throughput at 20 MHz

Data and Non-volatile Program and Data Memories

2K Bytes of In-System Self Programmable Flash

Endurance 10,000 Write/Erase Cycles

128 Bytes In-System Programmable EEPROM Endurance: 100,000 Write/Erase Cycles

128 Bytes Internal SRAM

Programming Lock for Flash Program and EEPROM Data Security

Peripheral Features

One 8-bit Timer/Counter with Separate Prescaler and Compare Mode

One 16-bit Timer/Counter with Separate Prescaler, Compare and Capture Modes

Four PWM Channels

On-chip Analog Comparator

Programmable Watchdog Timer with On-chip Oscillator

USI – Universal Serial Interface

Full Duplex USART

Special Microcontroller Features

debugWIRE On-chip Debugging

In-System Programmable via SPI Port

External and Internal Interrupt Sources

Low-power Idle, Power-down, and Standby Modes

Enhanced Power-on Reset Circuit

Programmable Brown-out Detection Circuit

Internal Calibrated Oscillator

I/O and Packages

18 Programmable I/O Lines

20-pin PDIP, 20-pin SOIC, 20-pad QFN/MLF

Operating Voltages

1.8 — 5.5V (ATtiny2313V)

2.7 — 5.5V (ATtiny2313)

Speed Grades

ATtiny2313V: 0 — 4 MHz @ 1.8 — 5.5V, 0 — 10 MHz @ 2.7 — 5.5V

ATtiny2313: 0 — 10 MHz @ 2.7 — 5.5V, 0 — 20 MHz @ 4.5 — 5.5V

Typical Power Consumption

Active Mode

1 MHz, 1.8V: 230 µA

32 kHz, 1.8V: 20 µA (including oscillator)

Power-down Mode

<0.1 µA at 1.8V

8-bit

Microcontroller with 2K Bytes In-System Programmable Flash

ATtiny2313/V

Preliminary

Rev. 2543H–AVR–02/05

Pin Configurations

Figure 1. Pinout ATtiny2313

PDIP/SOIC

VCC

(RESET/dW) PA2

1

20

(RXD) PD0

2

19

PB7 (UCSK/SCK/PCINT7)

(TXD) PD1

3

18

PB6 (MISO/DO/PCINT6)

(XTAL2) PA1

4

17

PB5 (MOSI/DI/SDA/PCINT5)

(XTAL1) PA0

5

16

PB4 (OC1B/PCINT4)

(CKOUT/XCK/INT0) PD2

6

15

PB3 (OC1A/PCINT3)

(INT1) PD3

7

14

PB2 (OC0A/PCINT2)

(T0) PD4

8

13

PB1 (AIN1/PCINT1)

(OC0B/T1) PD5

9

12

PB0 (AIN0/PCINT0)

GND

10

11

PD6 (ICP)

MLF

PA2 (RESET/dW)

PB7 (UCSK/SCK/PCINT7)

PB6 (MISO/DO/PCINT6)

PD0 (RXD)

VCC

(TXD) PD1

20

19

18

17

16

1

15

PB5 (MOSI/DI/SDA/PCINT5)

XTAL2) PA1

2

14

PB4 (OC1B/PCINT4)

(XTAL1) PA0

3

13

PB3 (OC1A/PCINT3)

(CKOUT/XCK/INT0) PD2

4

12

PB2 (OC0A/PCINT2)

(INT1) PD3

5

11

PB1 (AIN1/PCINT1)

6

7

8

9

10

(T0) PD4

(OC0B/T1) PD5

GND

(ICP) PD6

(AIN0/PCINT0) PB0

NOTE: Bottom pad should be soldered to ground.

Overview

The ATtiny2313 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny2313 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

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ATMEL ATtiny2313 User Manual

ATtiny2313/V

Block Diagram

Figure 2.

Block Diagram

XTAL1

XTAL2

PA0 — PA2

PORTA DRIVERS

VCC

DATA REGISTER

DATA DIR.

INTERNAL

PORTA

REG. PORTA

CALIBRATED

OSCILLATOR

8-BIT DATA BUS

INTERNAL

OSCILLATOR

OSCILLATOR

GND

PROGRAM

STACK

WATCHDOG

TIMING AND

RESET

COUNTER

POINTER

TIMER

CONTROL

MCU CONTROL

PROGRAM

SRAM

REGISTER

FLASH

MCU STATUS

ON-CHIP

DEBUGGER

REGISTER

INSTRUCTION

GENERAL

REGISTER

PURPOSE

TIMER/

REGISTER

COUNTERS

INSTRUCTION

INTERRUPT

DECODER

UNIT

EEPROM

CONTROL

ALU

LINES

USI

STATUS

REGISTER

PROGRAMMING

SPI

USART

LOGIC

ANALOG COMPARATOR

DATA REGISTER

DATA DIR.

DATA REGISTER

DATA DIR.

PORTB

REG. PORTB

PORTD

REG. PORTD

PORTB DRIVERS

PORTD DRIVERS

PB0 — PB7

PD0 — PD6

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The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATtiny2313 provides the following features: 2K bytes of In-System Programmable Flash, 128 bytes EEPROM, 128 bytes SRAM, 18 general purpose I/O lines, 32 general purpose working registers, a single-wire Interface for On-chip Debugging, two flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, a programmable Watchdog Timer with internal Oscillator, and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, or by a conventional non-volatile memory programmer. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATtiny2313 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATtiny2313 AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Cir- cuit Emulators, and Evaluation kits.

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ATtiny2313/V

Pin Descriptions

VCC

Digital supply voltage.

GND

Ground.

Port A (PA2..PA0)

Port A is a 3-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATtiny2313 as listed

on page 52.

Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port B pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny2313 as listed

on page 52.

Port D (PD6..PD0)

Port D is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port D pins that are externally pulled low will source

current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset

condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATtiny2313 as listed

on page 55.

Reset input. A low level on this pin for longer than the minimum pulse length will gener-

RESET

ate a reset, even if the clock is not running. The minimum pulse length is given in Table

15 on page 33. Shorter pulses are not guaranteed to generate a reset. The Reset Input

is an alternate function for PA2 and dW.

XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL1 is an alternate function for PA0.

XTAL2

Output from the inverting Oscillator amplifier. XTAL2 is an alternate function for PA1.

About Code

This documentation contains simple code examples that briefly show how to use various

Examples

parts of the device. These code examples assume that the part specific header file is

included before compilation. Be aware that not all C compiler vendors include bit defini-

tions in the header files and interrupt handling in C is compiler dependent. Please

confirm with the C compiler documentation for more details.

Disclaimer

Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

AVR CPU Core

Introduction

Architectural Overview

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 3. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash

Program

Status

Counter

and Control

Program

Memory

32 x 8

Interrupt

Instruction

Unit

General

Register

Purpose

SPI

Registrers

Unit

Instruction

Watchdog

Decoder

AddressingDirect

AddressingIndirect

Timer

ALU

Analog

Control Lines

Comparator

I/O Module1

Data

I/O Module 2

SRAM

I/O Module n

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture

– with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is InSystem Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File,

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ATtiny2313/V

ALU – Arithmetic Logic

Unit

the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16or 32-bit instruction.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 — 0x5F.

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-func- tions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be handled by software.

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The AVR Status Register – SREG – is defined as:

Bit

7

6

5

4

3

2

1

0

I

T

H

S

V

N

Z

C

SREG

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

General Purpose

Register File

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I- bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

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ATtiny2313/V

Figure 4. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

0x00

R1

0x01

R2

0x02

R13

0x0D

General

R14

0x0E

Purpose

R15

0x0F

Working

R16

0x10

Registers

R17

0x11

R26

0x1A

X-register Low Byte

R27

0x1B

X-register High Byte

R28

0x1C

Y-register Low Byte

R29

0x1D

Y-register High Byte

R30

0x1E

Z-register Low Byte

R31

0x1F

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

The X-register, Y-register, and The registers R26..R31 have some added functions to their general purpose usage. Z-register These registers are 16-bit address pointers for indirect addressing of the data space.

The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5.

The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

0

R27 (0x1B)

R26 (0x1A)

15

YH

YL

0

Y-register

7

0

7

0

R29 (0x1D)

R28 (0x1C)

15

ZH

ZL

0

Z-register

7

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

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Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit

15

14

13

12

11

10

9

8

SPH

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SPL

7

6

5

4

3

2

1

0

Read/Write

R

R

R

R

R

R

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the chip. No internal clock division is used.

Figure 6 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Parallel Instruction Fetches and Instruction Executions

clkCPU

1st Instruction Fetch

1st Instruction Execute 2nd Instruction Fetch 2nd Instruction Execute 3rd Instruction Fetch 3rd Instruction Execute 4th Instruction Fetch

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.

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Reset and Interrupt

Handling

ATtiny2313/V

Figure 7. Single Cycle ALU Operation

clkCPU Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 43. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0

– the External Interrupt Request 0. Refer to “Interrupts” on page 43 for more information.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have interrupt flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simulta-

neously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

;note: will enter sleep before any pending

;interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

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AVR ATtiny2313

Memories

In-System

Reprogrammable Flash

Program Memory

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ATtiny2313/V

This section describes the different memories in the ATtiny2313. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATtiny2313 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

The ATtiny2313 contains 2K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 1K x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny2313 Program Counter (PC) is 10 bits wide, thus addressing the 1K program memory locations. “Memory Programming” on page 158 contains a detailed description on Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 10.

Figure 8. Program Memory Map

Program Memory

0x0000

0x03FF

13

SRAM Data Memory

Figure 9 shows how the ATtiny2313 SRAM Memory is organized.

The lower 224 data memory locations address both the Register File, the I/O memory, Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standard I/O memory, and the next 128 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and postincrement, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128 bytes of internal data SRAM in the ATtiny2313 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 8.

Figure 9. Data Memory Map

Data Memory

32 Registers

64 I/O Registers

Internal SRAM

(128 x 8)

0x0000 — 0x001F

0x0020 — 0x005F

0x0060

0x00DF

Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clkCPU cycles as described in Figure 10.

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Figure 10. On-chip Data SRAM Access Cycles

T1 T2 T3

clkCPU

Address Compute Address Address valid

Data

WR

Data

RD

Read Write

Memory Access Instruction

Next Instruction

EEPROM Data Memory

EEPROM Read/Write Access

The EEPROM Address

Register

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The ATtiny2313 contains 128 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register. For a detailed description of Serial data downloading to the EEPROM, see page 172.

The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page 19. for details on how to avoid problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

Bit

7

6

5

4

3

2

1

0

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

EEAR0

EEAR

Read/Write

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

X

X

X

X

X

X

X

• Bit 7 – Res: Reserved Bit

This bit is reserved in the ATtiny2313 and will always read as zero.

15

The EEPROM Data Register –

EEDR

• Bits 6..0 – EEAR6..0: EEPROM Address

The EEPROM Address Register – EEAR specify the EEPROM address in the 128 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 127. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

Bit

7

6

5

4

3

2

1

0

MSB

LSB

EEDR

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

• Bits 7..0 – EEDR7..0: EEPROM Data

The EEPROM Control Register

– EECR

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

Bit

7

6

5

4

3

2

1

0

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

EECR

Read/Write

R

R

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

X

X

0

0

X

0

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny2313 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 1. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 1. EEPROM Mode Bits

Programming

EEPM1

EEPM0

Time

Operation

0

0

3.4 ms

Erase and Write in one operation (Atomic Operation)

0

1

1.8 ms

Erase Only

1

0

1.8 ms

Write Only

1

1

Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant interrupt when Non-volatile memory is ready for programming.

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ATtiny2313/V

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at

the selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE

has been written to one by software, hardware clears the bit to zero after four clock

cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the

EEPROM. When EEPE is written, the EEPROM will be programmed according to the

EEPMn bits setting. The EEMPE bit must be written to one before a logical one is writ-

ten to EEPE, otherwise no EEPROM write takes place. When the write access time has

elapsed, the EEPE bit is cleared by hardware. When EEPE has been set, the CPU is

halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When

the correct address is set up in the EEAR Register, the EERE bit must be written to one

to trigger the EEPROM read. The EEPROM read access takes one instruction, and the

requested data is available immediately. When the EEPROM is read, the CPU is halted

for four cycles before the next instruction is executed. The user should poll the EEPE bit

before starting the read operation. If a write operation is in progress, it is neither possible

to read the EEPROM, nor to change the EEAR Register.

Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the

EEPROM, the user must write the address into the EEAR Register and data into EEDR

Register. If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is

written) will trigger the erase/write operation. Both the erase and write cycle are done in

one operation and the total programming time is given in Table 1. The EEPE bit remains

set until the erase and write operations are completed. While the device is busy with

programming, it is not possible to do any other EEPROM operations.

Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be

useful if the system requires short access time for some limited period of time (typically

if the power supply voltage falls). In order to take advantage of this method, it is required

that the locations to be written have been erased before the write operation. But since

the erase and write operations are split, it is possible to do the erase operations when

the system allows doing time-consuming operations (typically after Power-up).

Erase

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writ-

ing the EEPE (within four cycles after EEMPE is written) will trigger the erase operation

only (programming time is given in Table 1). The EEPE bit remains set until the erase

operation completes. While the device is busy programming, it is not possible to do any

other EEPROM operations.

Write

To write a location, the user must write the address into EEAR and the data into EEDR.

If the EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written)

will trigger the write operation only (programming time is given in Table 1). The EEPE bit

remains set until the write operation completes. If the location to be written has not been

erased before write, the data that is stored must be considered as lost. While the device

is busy with programming, it is not possible to do any other EEPROM operations.

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The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator frequency is within the requirements described in “Oscillator Calibration Register – OSCCAL” on page 25.

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r17) in address register out EEAR, r17

; Write data (r16) to data register out EEDR,r16

; Write logical one to EEMPE sbi EECR,EEMPE

; Start eeprom write by setting EEPE sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */ while(EECR & (1<<EEPE))

;

/* Set up address and data registers */ EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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ATtiny2313/V

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r17) in address register

out

EEAR, r17

; Start eeprom read by writing EERE

sbi

EECR,EERE

; Read data from data register

in

r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

Preventing EEPROM

During periods of low VCC, the EEPROM data can be corrupted because the supply volt-

Corruption

age is too low for the CPU and the EEPROM to operate properly. These issues are the

same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

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I/O Memory

The I/O space definition of the ATtiny2313 is shown in “Register Summary” on page

211.

All ATtiny2313 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between

the 32 general purpose working registers and the I/O space. I/O Registers within the

address range 0x00 — 0x1F are directly bit-accessible using the SBI and CBI instruc-

tions. In these registers, the value of single bits can be checked by using the SBIS and

SBIC instructions. Refer to the instruction set section for more details. When using the

I/O specific commands IN and OUT, the I/O addresses 0x00 — 0x3F must be used.

When addressing I/O Registers as data space using LD and ST instructions, 0x20 must

be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike

most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and

can therefore be used on registers containing such status flags. The CBI and SBI

instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

General Purpose I/O Registers The ATtiny2313 contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and status flags. General Purpose I/O Registers within the address range 0x00 — 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

General Purpose I/O Register

2 – GPIOR2

General Purpose I/O Register

1 – GPIOR1

General Purpose I/O Register

0 – GPIOR0

Bit

7

6

5

4

3

2

1

0

MSB

LSB

GPIOR2

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

MSB

LSB

GPIOR1

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

Bit

7

6

5

4

3

2

1

0

MSB

LSB

GPIOR0

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

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ATtiny2313/V

System Clock and

Clock Options

Clock Systems and their Distribution

Figure 11 presents the principal clock systems in the AVR and their distribution. All of the clocks need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 29. The clock systems are detailed below.

Figure 11. Clock Distribution

General I/O

CPU Core

RAM

Flash and

Modules

EEPROM

clkI/O

AVR Clock

clkCPU

Control Unit

clkFLASH

Reset Logic

Watchdog Timer

Source clock

Watchdog clock

Clock

Multiplexer

Watchdog

Oscillator

External Clock

Crystal

Calibrated RC

Oscillator

Oscillator

CPU Clock – clkCPU

The CPU clock is routed to parts of the system concerned with operation of the AVR

core. Examples of such modules are the General Purpose Register File, the Status Reg-

ister and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the

core from performing general operations and calculations.

I/O Clock – clkI/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, and

USART. The I/O clock is also used by the External Interrupt module, but note that some

external interrupts are detected by asynchronous logic, allowing such interrupts to be

detected even if the I/O clock is halted. Also note that start condition detection in the USI

module is carried out asynchronously when clkI/O is halted, enabling USI start condition

detection in all sleep modes.

Flash Clock – clkFLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually

active simultaneously with the CPU clock.

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Clock Sources

Default Clock Source

Crystal Oscillator

The device has the following clock source options, selectable by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 2. Device Clocking Select(1)

Device Clocking Option

CKSEL3..0

External Clock

0000

Calibrated Internal RC Oscillator 4MHz

0010

Calibrated internal RC Oscillator 8MHz

0100

Watchdog Oscillator 128kHz

0110

External Crystal/Ceramic Resonator

1000 — 1111

Reserved

0001/0011/0101/0111

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU wakes up from Power-down, the selected clock source is used to time the start-up, ensuring stable Oscillator operation before instruction execution starts. When the CPU starts from reset, there is an additional delay allowing the power to reach a stable level before commencing normal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time. The number of WDT Oscillator cycles used for each time-out is shown in Table 3. The frequency of the Watchdog Oscillator is voltage dependent as shown in “ATtiny2313 Typical Characteristics” on page 181.

Table 3. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V)

Typ Time-out (VCC = 3.0V)

Number of Cycles

4.1 ms

4.3 ms

4K

(4,096)

65 ms

69 ms

64K

(65,536)

The device is shipped with CKSEL = “0100”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. This default setting ensures that all users can make their desired clock source setting using an In-System or Parallel programmer.

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 12 on page 23. Either a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 4 on page 23. For ceramic resonators, the capacitor values given by the manufacturer should be used.

22 ATtiny2313/V

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ATtiny2313/V

Figure 12. Crystal Oscillator Connections

C2

XTAL2

C1

XTAL1

GND

The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 4.

Table 4. Crystal Oscillator Operating Modes

Frequency Range(1) (MHz)

Recommended Range for Capacitors C1

CKSEL3..1

and C2 for Use with Crystals (pF)

100(2)

0.4 — 0.9

101

0.9 — 3.0

12 — 22

110

3.0 — 8.0

12 — 22

111

8.0 —

12 — 22

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table 5.

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Calibrated Internal RC

Oscillator

Table 5. Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from

Additional Delay

Power-down and

from Reset

CKSEL0

SUT1..0

Power-save

(VCC = 5.0V)

Recommended Usage

0

00

258 CK(1)

14CK + 4.1 ms

Ceramic resonator, fast

rising power

0

01

258 CK(1)

14CK + 65 ms

Ceramic resonator,

slowly rising power

0

10

1K CK(2)

14CK

Ceramic resonator,

BOD enabled

0

11

1K CK(2)

14CK + 4.1 ms

Ceramic resonator, fast

rising power

1

00

1K CK(2)

14CK + 65 ms

Ceramic resonator,

slowly rising power

1

01

16K CK

14CK

Crystal Oscillator, BOD

enabled

1

10

16K CK

14CK + 4.1 ms

Crystal Oscillator, fast

rising power

1

11

16K CK

14CK + 65 ms

Crystal Oscillator,

slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2.These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

The calibrated internal RC Oscillator provides a fixed 8.0 MHz clock. The frequency is nominal value at 3V and 25°C. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse must be programmed in order to divide the internal frequency by 8 during start-up. The device is shipped with the CKDIV8 Fuse programmed. This clock may be selected as the system clock by programming the CKSEL Fuses as shown in Table 6. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives a frequency within ± 10% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 2% accuracy at any given VCC and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 160.

Table 6. Internal Calibrated RC Oscillator Operating Modes

CKSEL3..0

Nominal Frequency

0010 — 0011

4.0 MHz

0100 — 0101

8.0 MHz(1)

Note: 1. The device is shipped with this option selected.

24 ATtiny2313/V

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ATtiny2313/V

Oscillator Calibration Register

– OSCCAL

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in Table 7.

Table 7. Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

Additional Delay from

SUT1..0

down and Power-save

Reset (VCC = 5.0V)

Recommended Usage

00

6 CK

14CK

BOD enabled

01

6 CK

14CK + 4.1 ms

Fast rising power

10(1)

6 CK

14CK + 65 ms

Slowly rising power

11

Reserved

Note: 1.

The device is shipped with this option selected.

Bit

7

6

5

4

3

2

1

0

CAL6

CAL5

CAL4

CAL3

CAL2

CAL1

CAL0

OSCCAL

Read/Write

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

Device Specific Calibration Value

• Bits 6..0 – CAL6..0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal Oscillator to remove process variations from the Oscillator frequency. This is done automatically during Chip Reset. When OSCCAL is zero, the lowest available frequency is chosen. Writing nonzero values to this register will increase the frequency of the internal Oscillator. Writing 0x7F to the register gives the highest available frequency. The calibrated Oscillator is used to time EEPROM and Flash access. If EEPROM or Flash is written, do not calibrate to more than 10% above the nominal frequency. Otherwise, the EEPROM or Flash write may fail. Note that the Oscillator is intended for calibration to 8.0/4.0 MHz. Tuning to other values is not guaranteed, as indicated in Table 8.

Avoid changing the calibration value in large steps when calibrating the Calibrated Internal RC Oscillator to ensure stable operation of the MCU. A variation in frequency of more than 2% from one cycle to the next can lead to unpredictable behavior. Changes in OSCCAL should not exceed 0x20 for each calibration.

Table 8. Internal RC Oscillator Frequency Range.

Min Frequency in Percentage of

Max Frequency in Percentage of

OSCCAL Value

Nominal Frequency

Nominal Frequency

0x00

50%

100%

0x3F

75%

150%

0x7F

100%

200%

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External Clock

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure 13. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

Figure 13. External Clock Drive Configuration

EXTERNAL

CLOCK XTAL1

SIGNAL

GND

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 10.

Table 9. Crystal Oscillator Clock Frequency

CKSEL3..0

Frequency Range

0000 — 0001

0 — 16 MHz

Table 10. Start-up Times for the External Clock Selection

Start-up Time from Power-

Additional Delay from

SUT1..0

down and Power-save

Reset (VCC = 5.0V)

Recommended Usage

00

6 CK

14CK

BOD enabled

01

6 CK

14CK + 4.1 ms

Fast rising power

10

6 CK

14CK + 65 ms

Slowly rising power

11

Reserved

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation.

26 ATtiny2313/V

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128 kHz Internal

Oscillator

Clock Prescale Register –

CLKPR

2543H–AVR–02/05

ATtiny2313/V

The 128 kHz Internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3 V and 25°C. This clock may be selected as the system clock by programming the CKSEL Fuses to “0110 — 0111”.

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 11.

Table 11. Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from Power-

Additional Delay from

SUT1..0

down and Power-save

Reset

Recommended Usage

00

6 CK

14CK

BOD enabled

01

6 CK

14CK + 4 ms

Fast rising power

10

6 CK

14CK + 64 ms

Slowly rising power

11

Reserved

Bit

7

6

5

4

3

2

1

0

CLKPCE

CLKPS3

CLKPS2

CLKPS1

CLKPS0

CLKPR

Read/Write

R/W

R

R

R

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 — 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in Table 12.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1.Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2.Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher

27

frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 12. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

0

0

0

1

0

0

0

1

2

0

0

1

0

4

0

0

1

1

8

0

1

0

0

16

0

1

0

1

32

0

1

1

0

64

0

1

1

1

128

1

0

0

0

256

1

0

0

1

Reserved

1

0

1

0

Reserved

1

0

1

1

Reserved

1

1

0

0

Reserved

1

1

0

1

Reserved

1

1

1

0

Reserved

1

1

1

1

Reserved

28 ATtiny2313/V

2543H–AVR–02/05

Power Management

and Sleep Modes

MCU Control Register –

MCUCR

Idle Mode

2543H–AVR–02/05

ATtiny2313/V

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.

To enter any of the three sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM1 and SM0 bits in the MCUCR Register select which sleep mode (Idle, Power-down, or Standby) will be activated by the SLEEP instruction. See Table 13 for a summary. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Figure 11 on page 21 presents the different clock systems in the ATtiny2313, and their distribution. The figure is helpful in selecting an appropriate sleep mode.

The Sleep Mode Control Register contains control bits for power management.

Bit

7

6

5

4

3

2

1

0

PUD

SM1

SE

SM0

ISC11

ISC10

ISC01

ISC00

MCUCR

Read/Write

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

• Bits 6, 4 – SM1..0: Sleep Mode Select Bits 1 and 0

These bits select between the five available sleep modes as shown in Table 13.

Table 13. Sleep Mode Select

SM1

SM0

Sleep Mode

0

0

Idle

0

1

Power-down

1

1

Power-down

1

0

Standby

Note: 1.

Standby mode is only recommended for use with external crystals or resonators.

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of the SLEEP instruction and to clear it immediately after waking up.

When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the UART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and UART Transmit Complete interrupts. If wakeup from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode.

29

Power-down Mode

Standby Mode

When the SM1..0 bits are written to 01 or 11, the SLEEP instruction makes the MCU enter Power-down mode. In this mode, the external Oscillator is stopped, while the external interrupts, the USI start condition detection, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, USI start condition interrupt, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 58 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Clock Sources” on page 22.

When the SM1..0 bits are 10 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.

Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains

Oscillators

Wake-up Sources

Sleep Mode

clk

clk

clk

Enabled

INT0,INT1 and PinChange

USIStart Condition

SPM/EEPROM Ready

OtherI/O

CPU

FLASH

IO

Idle

X

X

X

X

X

X

Power-down

X(2)

X

Standby(1)

X

X(2)

X

Notes: 1. Only recommended with external crystal or resonator selected as clock source. 2. For INT0, only level interrupt.

Minimizing Power

Consumption

Analog Comparator

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

When entering Idle mode, the Analog Comparator should be disabled if not used. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep mode. Refer to “Analog Comparator” on page 149 for details on how to configure the Analog Comparator.

30 ATtiny2313/V

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ATtiny2313/V

Brown-out Detector

If the Brown-out Detector is not needed by the application, this module should be turned

off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in

all sleep modes, and hence, always consume power. In the deeper sleep modes, this

will contribute significantly to the total current consumption. Refer to “Brown-out Detec-

tion” on page 34 for details on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detec-

tion or the Analog Comparator. If these modules are disabled as described in the

sections above, the internal voltage reference will be disabled and it will not be consum-

ing power. When turned on again, the user must allow the reference to start up before

the output is used. If the reference is kept on in sleep mode, the output can be used

immediately. Refer to “Internal Voltage Reference” on page 37 for details on the start-up

time.

Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off.

If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence,

always consume power. In the deeper sleep modes, this will contribute significantly to

the total current consumption. Refer to “Interrupts” on page 43 for details on how to con-

figure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power.

The most important is then to ensure that no pins drive resistive loads. In sleep modes

where the I/O clock (clkI/O) is stopped, the input buffers of the device will be disabled.

This ensures that no power is consumed by the input logic when not needed. In some

cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 49 for

details on which pins are enabled. If the input buffer is enabled and the input signal is

left floating or have an analog signal level close to VCC/2, the input buffer will use exces-

sive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog

signal level close to VCC/2 on an input pin can cause significant current even in active

mode. Digital input buffers can be disabled by writing to the Digital Input Disable Regis-

ters (DIDR). Refer to “Digital Input Disable Register – DIDR” on page 150.

31

2543H–AVR–02/05

System Control and

Reset

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts exe-

cution from the Reset Vector. The instruction placed at the Reset Vector must be an

RJMP – Relative Jump – instruction to the reset handling routine. If the program never

enables an interrupt source, the Interrupt Vectors are not used, and regular program

code can be placed at these locations. The circuit diagram in Figure 14 shows the reset

logic. Table 15 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source

goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the

internal reset. This allows the power to reach a stable level before normal operation

starts. The time-out period of the delay counter is defined by the user through the SUT

and CKSEL Fuses. The different selections for the delay period are presented in “Clock

Sources” on page 22.

Reset Sources

The ATtiny2313 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (VPOT).

• External Reset. The MCU is reset when a low level is present on the

RESET

pin for

longer than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires, the

Watchdog is enabled, and Watchdog Interrupt is disabled.

• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the

Brown-out Reset threshold (VBOT) and the Brown-out Detector is enabled.

Figure 14. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

PORF

BORF

EXTRF

WDRF

Power-on Reset

Circuit

BODLEVEL [2..0]

Brown-out

Reset Circuit

Pull-up Resistor

SPIKE

FILTER

Watchdog

Oscillator

Delay Counters

Clock

CK

Generator

TIMEOUT

CKSEL[3:0]

SUT[1:0]

32 ATtiny2313/V

2543H–AVR–02/05

ATtiny2313/V

Table 15.

Reset Characteristics

Symbol

Parameter

Condition

Min(1)

Typ(1)

Max(1)

Units

Power-on Reset

TA = -40 — 85°C

Threshold Voltage

1.2

V

VPOT

(rising)

Power-on Reset

TA = -40 — 85°C

Threshold Voltage

1.1

V

(falling)(2)

Pin Threshold

VRST

RESET

VCC

= 1.8 — 5.5V

0.2 VCC

0.9 VCC

V

Voltage

tRST

Minimum pulse width

VCC

= 1.8 — 5.5V

2.5

µs

on

Pin

RESET

Notes: 1. Values are guidelines only. Actual values are TBD.

2. The Power-on Reset will not work unless the supply voltage has been below VPOT

(falling)

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec-

tion level is defined in Table 15. The POR is activated whenever VCC is below the

detection level. The POR circuit can be used to trigger the start-up Reset, as well as to

detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reach-

ing the Power-on Reset threshold voltage invokes the delay counter, which determines

how long the device is kept in RESET after VCC rise. The RESET signal is activated

again, without any delay, when VCC decreases below the detection level.

Figure 15. MCU Start-up,

Tied to VCC

RESET

VCC

VPOT

VRST

RESET

TIME-OUT

tTOUT

INTERNAL

RESET

33

2543H–AVR–02/05

Figure 16. MCU Start-up, RESET Extended Externally

VPOT

VCC

VRST

RESET

tTOUT

TIME-OUT

INTERNAL

External Reset

RESET

An External Reset is generated by a low level on the

pin. Reset pulses longer

RESET

than the minimum pulse width (see Table 15) will generate a reset, even if the clock is

not running. Shorter pulses are not guaranteed to generate a reset. When the applied

signal reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay

counter starts the MCU after the Time-out period – tTOUT – has expired.

Figure 17. External Reset During Operation

CC

Brown-out Detection

ATtiny2313 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC

level during operation by comparing it to a fixed trigger level. The trigger level for the

BOD can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to

ensure spike free Brown-out Detection. The hysteresis on the detection level should be

interpreted as VBOT+ = VBOT + VHYST/2 and VBOT- = VBOT — VHYST/2.

Table 16. BODLEVEL Fuse Coding(1)

BODLEVEL 2..0 Fuses

Min VBOT

Typ VBOT

Max VBOT

Units

111

BOD Disabled

110

1.8

101

2.7

V

100

4.3

34 ATtiny2313/V

2543H–AVR–02/05

ATtiny2313/V

Table 16. BODLEVEL Fuse Coding(1)

BODLEVEL 2..0 Fuses

Min VBOT

Typ VBOT

Max VBOT

Units

011

010

Reserved

001

000

Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 for ATtiny2313V and BODLEVEL = 101 for ATtiny2313L.

Table 17. Brown-out Characteristics

Symbol

Parameter

Min

Typ

Max

Units

VHYST

Brown-out Detector Hysteresis

50

mV

tBOD

Min Pulse Width on Brown-out Reset

2

ns

When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure 18), the Brown-out Reset is immediately activated. When VCC increases above

the trigger level (VBOT+ in Figure 18), the delay counter starts the MCU after the Timeout period tTOUT has expired.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in Table 15.

Figure 18. Brown-out Reset During Operation

VCC

VBOT+

VBOT-

RESET

TIME-OUT

tTOUT

INTERNAL

RESET

35

2543H–AVR–02/05

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

tTOUT. Refer to page 43 for details on operation of the Watchdog Timer.

Figure 19. Watchdog Reset During Operation

CC

CK

MCU Status Register –

The MCU Status Register provides information on which reset source caused an MCU

MCUSR

reset.

Bit

7

6

5

4

3

2

1

0

WDRF

BORF

EXTRF

PORF

MCUSR

Read/Write

R

R

R

R

R/W

R/W

R/W

R/W

Initial Value

0

0

0

See Bit Description

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset flags to identify a reset condition, the user should read and then reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags.

36 ATtiny2313/V

2543H–AVR–02/05

ATtiny2313/V

Internal Voltage

ATtiny2313 features an internal bandgap reference. This reference is used for Brown-

Reference

out Detection, and it can be used as an input to the Analog Comparator.

Voltage Reference Enable The voltage reference has a start-up time that may influence the way it should be used. Signals and Start-up Time The start-up time is given in Table 18. To save power, the reference is not always turned on. The reference is on during the following situations:

1.When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2.When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

Thus, when the BOD is not enabled, after setting the ACBG bit, the user must always allow the reference to start up before the output from the Analog Comparator is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

Table 18. Internal Voltage Reference Characteristics(1)

Symbol

Parameter

Condition

Min

Typ

Max

Units

VBG

Bandgap reference voltage

VCC = 2.7V,

1.0

1.1

1.2

V

TA = 25°C

tBG

Bandgap reference start-up time

VCC = 2.7V,

40

70

µs

TA = 25°C

IBG

Bandgap reference current

VCC = 2.7V,

15

µA

consumption

TA = 25°C

Note: 1.

Values are guidelines only. Actual values are TBD.

37

2543H–AVR–02/05

Watchdog Timer

ATtiny2313 has an Enhanced Watchdog Timer (WDT). The main features are:

Clocked from separate On-chip Oscillator

3 Operating modes

Interrupt

System Reset

Interrupt and System Reset

Selectable Time-out period from 16ms to 8s

Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

Figure 20. Watchdog Timer

128kHz

OSCILLATOR

OSC/2K OSC/4K OSC/8K OSC/16K OSC/32K OSC/64K OSC/128K OSC/256K OSC/512K OSC/1024K

WDP0

WATCHDOG

WDP1

WDP2

RESET

WDP3

WDE

MCU RESET

WDIF

WDIE

INTERRUPT

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR — Watchdog Timer Reset — instruction to restart the counter before the time-out value is reached. If the system doesn’t restart the counter, an interrupt or system reset will be issued.

In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively.

To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows:

1.In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2.Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as desired, but with the WDCE bit cleared. This must be done in one operation.

38 ATtiny2313/V

2543H–AVR–02/05

ATtiny2313/V

The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.

Assembly Code Example(1)

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer wdr

; Clear WDRF in MCUSR

in r16, MCUSR

andi r16, (0xff & (0<<WDRF)) out MCUSR, r16

;Write logical one to WDCE and WDE

;Keep old prescaler setting to prevent unintentional time-out

in

r16, WDTCSR

ori

r16, (1<<WDCE) | (1<<WDE)

out

WDTCSR, r16

; Turn off WDT

ldi

r16, (0<<WDE)

out

WDTCSR, r16

; Turn on global interrupt

sei

ret

C Code Example(1)

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out

*/

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

__enable_interrupt();

}

Note: 1.

The example code assumes that the part specific header file is included.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the

39

2543H–AVR–02/05

Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.

Assembly Code Example(1)

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer wdr

; Start timed sequence in r16, WDTCSR

ori r16, (1<<WDCE) | (1<<WDE) out WDTCSR, r16

; Got four cycles to set the new values from here —

;Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0) out WDTCSR, r16

; Finished setting new values, used 2 cycles —

;Turn on global interrupt

sei ret

C Code Example(1)

void WDT_Prescaler_Change(void)

{

__disable_interrupt(); __watchdog_reset();

/* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */ WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt();

}

Note: 1. The example code assumes that the part specific header file is included.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period.

40 ATtiny2313/V

2543H–AVR–02/05

Watchdog Timer Control

Register — WDTCSR

2543H–AVR–02/05

ATtiny2313/V

Bit

7

6

5

4

3

2

1

0

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

WDTCSR

Read/Write

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Initial Value

0

0

0

0

X

0

0

0

• Bit 7 — WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 — WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.

Table 19. Watchdog Timer Configuration

WDTON

WDE

WDIE

Mode

Action on Time-out

0

0

0

Stopped

None

0

0

1

Interrupt Mode

Interrupt

0

1

0

System Reset Mode

Reset

0

1

1

Interrupt and System

Interrupt, then go to

Reset Mode

System Reset Mode

1

x

x

System Reset Mode

Reset

• Bit 4 — WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 — WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 — WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in Table 20 on page 42.

41

Table 20. Watchdog Timer Prescale Select

Number of WDT Oscillator

Typical Time-out at

WDP3

WDP2

WDP1

WDP0

Cycles

VCC = 5.0V

0

0

0

0

2K

(2048) cycles

16 ms

0

0

0

1

4K

(4096) cycles

32 ms

0

0

1

0

8K

(8192) cycles

64 ms

0

0

1

1

16K

(16384) cycles

0.125 s

0

1

0

0

32K

(32768) cycles

0.25 s

0

1

0

1

64K

(65536) cycles

0.5 s

0

1

1

0

128K

(131072) cycles

1.0 s

0

1

1

1

256K

(262144) cycles

2.0 s

1

0

0

0

512K

(524288) cycles

4.0 s

1

0

0

1

1024K

(1048576) cycles

8.0 s

1

0

1

0

1

0

1

1

1

1

0

0

Reserved

1

1

0

1

1

1

1

0

1

1

1

1

42 ATtiny2313/V

2543H–AVR–02/05

Interrupts

Interrupt Vectors in

ATtiny2313

2543H–AVR–02/05

ATtiny2313/V

This section describes the specifics of the interrupt handling as performed in ATtiny2313. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 11.

Table 21. Reset and Interrupt Vectors

Vector

Program

No.

Address

Source

Interrupt Definition

1

0x0000

RESET

External Pin, Power-on Reset, Brown-out Reset,

and Watchdog Reset

2

0x0001

INT0

External Interrupt Request 0

3

0x0002

INT1

External Interrupt Request 1

4

0x0003

TIMER1 CAPT

Timer/Counter1 Capture Event

5

0x0004

TIMER1 COMPA

Timer/Counter1 Compare Match A

6

0x0005

TIMER1 OVF

Timer/Counter1 Overflow

7

0x0006

TIMER0 OVF

Timer/Counter0 Overflow

8

0x0007

USART0, RX

USART0, Rx Complete

9

0x0008

USART0, UDRE

USART0 Data Register Empty

10

0x0009

USART0, TX

USART0, Tx Complete

11

0x000A

ANALOG COMP

Analog Comparator

12

0x000B

PCINT

Pin Change Interrupt

13

0x000C

TIMER1 COMPB

Timer/Counter1 Compare Match B

14

0x000D

TIMER0 COMPA

Timer/Counter0 Compare Match A

15

0x000E

TIMER0 COMPB

Timer/Counter0 Compare Match B

16

0x000F

USI START

USI Start Condition

17

0x0010

USI OVERFLOW

USI Overflow

18

0x0011

EE READY

EEPROM Ready

19

0x0012

WDT OVERFLOW

Watchdog Timer Overflow

43

The most typical and general program setup for the Reset and Interrupt Vector

Addresses in ATtiny2313 is:

Address

Labels Code

Comments

0x0000

rjmp

RESET

; Reset Handler

0x0001

rjmp

INT0

; External Interrupt0 Handler

0x0002

rjmp

INT1

; External Interrupt1 Handler

0x0003

rjmp

TIM1_CAPT

; Timer1 Capture Handler

0x0004

rjmp

TIM1_COMPA

; Timer1 CompareA Handler

0x0005

rjmp

TIM1_OVF

; Timer1 Overflow Handler

0x0006

rjmp

TIM0_OVF

; Timer0 Overflow Handler

0x0007

rjmp

USART0_RXC

; USART0 RX Complete Handler

0x0008

rjmp

USART0_DRE

; USART0,UDR Empty Handler

0x0009

rjmp

USART0_TXC

; USART0 TX Complete Handler

0x000A

rjmp

ANA_COMP

; Analog Comparator Handler

0x000B

rjmp

PCINT

; Pin Change Interrupt

0x000C

rjmp

TIMER1_COMPB

; Timer1 Compare B Handler

0x000D

rjmp

TIMER0_COMPA

; Timer0 Compare A Handler

0x000E

rjmp

TIMER0_COMPB

; Timer0 Compare B Handler

0x000F

rjmp

USI_START

; USI Start Handler

0x0010

rjmp

USI_OVERFLOW

; USI Overflow Handler

0x0011

rjmp

EE_READY

; EEPROM Ready Handler

0x0012

rjmp

WDT_OVERFLOW

; Watchdog Overflow Handler

;

0x0013

RESET: ldi

r16, low(RAMEND); Main program start

0x0014

out

SPL,r16

Set Stack Pointer to top of

RAM

0x0015

sei

; Enable interrupts

0x0016

<instr> xxx

… …

44 ATtiny2313/V

2543H–AVR–02/05

ATtiny2313/V

I/O-Ports

Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital

I/O ports. This means that the direction of one port pin can be changed without uninten-

tionally changing the direction of any other pin with the SBI and CBI instructions. The

same applies when changing drive value (if configured as output) or enabling/disabling

of pull-up resistors (if configured as input). Each output buffer has symmetrical drive

characteristics with both high sink and source capability. The pin driver is strong enough

to drive LED displays directly. All port pins have individually selectable pull-up resistors

with a supply-voltage invariant resistance. All I/O pins have protection diodes to both

VCC and Ground as indicated in Figure 21. Refer to “Electrical Characteristics” on page

177 for a complete list of parameters.

Figure 21. I/O Pin Equivalent Schematic

Rpu

Pxn

Logic

Cpin

See Figure

«General Digital I/O» for

Details

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 57.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page 46. Most port pins are multiplexed with alternate functions for the peripheral features on the device. How each alternate function interferes with the port pin is described in “Alternate Port Functions” on page 50. Refer to the individual module sections for a full description of the alternate functions.

45

2543H–AVR–02/05

Ports as General Digital

I/O

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 22 shows a functional description of one I/O-port pin, here generically called Pxn.

Figure 22. General Digital I/O(1)

PUD

Q

D

DDxn

Q CLR

RESET

WDx

RDx

Q

D

1

BUS

Pxn

DATA

PORTxn

0

Q CLR

RESET

WPx

WRx

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D Q

PINxn

L

Q

Q

clk I/O

PUD:

PULLUP DISABLE

WDx:

WRITE DDRx

RDx:

READ DDRx

SLEEP:

SLEEP CONTROL

WRx:

WRITE PORTx

clkI/O:

I/O CLOCK

RRx:

READ PORTx REGISTER

RPx:

READ PORTx PIN

WPx:

WRITE PINx REGISTER

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

clkI/O, SLEEP, and PUD are common to all ports.

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in

“Register Description for I/O-Ports” on page 57, the DDxn bits are accessed at the

DDRx I/O address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at

the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written

logic one, Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is config-

ured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up

resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic

zero or the pin has to be configured as an output pin. The port pins are tri-stated when

reset condition becomes active, even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is

driven high (one). If PORTxn is written logic zero when the pin is configured as an out-

put pin, the port pin is driven low (zero).

46 ATtiny2313/V

2543H–AVR–02/05

ATtiny2313/V

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of

DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn,

Output

PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} =

0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up

enabled state is fully acceptable, as a high-impedant environment will not notice the dif-

ference between a strong high driver and a pull-up. If this is not the case, the PUD bit in

the MCUCR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The

user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state

({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 22 summarizes the control signals for the pin value.

Table 22. Port Pin Configurations

PUD (in

DDxn

PORTxn

MCUCR2)

I/O

Pull-up

Comment

0

0

X

Input

No

Tri-state (Hi-Z)

Pxn will source current if ext. pulled

0

1

0

Input

Yes

low.

0

1

1

Input

No

Tri-state (Hi-Z)

1

0

X

Output

No

Output Low (Sink)

1

1

X

Output

No

Output High (Source)

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through

the PINxn Register bit. As shown in Figure 22, the PINxn Register bit and the preceding

latch constitute a synchronizer. This is needed to avoid metastability if the physical pin

changes value near the edge of the internal clock, but it also introduces a delay. Figure 23 shows a timing diagram of the synchronization when reading an externally applied

pin value. The maximum and minimum propagation delays are denoted tpd,max and tpd,min respectively.

Figure 23. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

SYNC LATCH

PINxn

r17

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 24. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 24. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

0xFF

out PORTx, r16

nop

in r17, PINx

tpd

48 ATtiny2313/V

2543H–AVR–02/05

ATtiny2313/V

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

Assembly Code Example(1)

;Define pull-ups and set outputs high

;Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0) ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0) out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins in r16,PINB

C Code Example

unsigned char i;

/* Define pull-ups and set outputs high */ /* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0); DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0); /* Insert nop for synchronization*/ __no_operation();

/* Read port pins */ i = PINB;

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

Digital Input Enable and Sleep As shown in Figure 22, the digital input signal can be clamped to ground at the input of Modes the Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, and Standby mode to avoid high power consumption if

some input signals are left floating, or have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 50.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

49

2543H–AVR–02/05

Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. Figure 25 shows how the port pin control signals from the simplified Figure 22 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

Figure 25. Alternate Port Functions(1)

PUOExn

1

PUOVxn

0

PUD

DDOExn

1

DDOVxn

0

Q

D

DDxn

Q CLR

PVOExn

RESET

WDx

PVOVxn

RDx

BUS

Pxn

1

1

0

Q

D

0

DATA

PORTxn

DIEOExn

Q CLR

PTOExn

WPx

1

DIEOVxn

RESET

WRx

RRx

0

SLEEP

SYNCHRONIZER

RPx

D SET

Q

D

Q

PINxn

L CLR

Q

CLR Q

clk I/O

DIxn

AIOxn

PUOExn:

Pxn PULL-UP OVERRIDE ENABLE

PUOVxn:

Pxn PULL-UP OVERRIDE VALUE

DDOExn:

Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn:

Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn:

Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn:

Pxn PORT VALUE OVERRIDE VALUE

DIEOExn:

Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn:

Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

SLEEP:

SLEEP CONTROL

PTOExn:

Pxn, PORT TOGGLE OVERRIDE ENABLE

PUD:

PULLUP DISABLE

WDx:

WRITE DDRx

RDx:

READ DDRx

RRx:

READ PORTx REGISTER

WRx:

WRITE PORTx

RPx:

READ PORTx PIN

WPx:

WRITE PINx

clk :

I/O CLOCK

I/O

DIGITAL INPUT PIN n ON PORTx

DIxn:

AIOxn:

ANALOG INPUT/OUTPUT PIN n ON PORTx

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port.

clkI/O, SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

Table 23 summarizes the function of the overriding signals. The pin and port indexes from Figure 25 are not shown in the succeeding tables. The overriding signals are generated internally in the modules having the alternate function.

50 ATtiny2313/V

2543H–AVR–02/05

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Introduction: How to Program ATtiny2313

Howdy folks!

When I first got my ATtiny2313 it took me the better part of 4 hours to finally get it programmed. I went through countless tutorials online that were old and outdated. I was never able to get the correct files from one website. I had to combine the files from several websites before I was finally able to program my ATtiny.

NOTE: With the recent update of the Arduino IDE I can’t figure out how to get the boards to show up in the list. I’m sure it’s easy and I’ll figure it out in a bit. For now you are still going to have to use the old version of arduino for programming any ATtiny chips.

The goal of my (Current and Updated!!!) series is to find tutorials online that are old, outdated, or nonworking and make a new tutorial that I have tested and used myself.
My first i’ble in this series is how to use IR remotes to control your Arduino.
I will keep updating my i’bles in this series to work with new Arduino boards, IDEs and the like.

Now I’ve never tested this process on a windows but I know that it works on a mac. It should be the same for windows, just delete any mac content in the zip.

Step 1: Download the Files

First you need to download the boards information for the Arduino IDE. This file will need to be downloaded in order to program a ATtiny2313. http://www.mediafire.com/download/ju012s124w4gbl2/tiny.zip

Once you have downloaded that you will need to extract the ‘tiny’ folder to your Arduino hardware folder. Now if you don’t know where that is or if you don’t have it here are the steps.

  • Go to your Arduino documents. This is where all the sketches are saved (by default).
  • For mac users it’s Macintosh HD>Users>username>documents>Arduino.
  • Create a new folder and name it «hardware», just like that. Into this folder you will put the ‘tiny’ folder that you downloaded.
  • For PC usersProgram Files(x86)=>Arduino=>hardware. Copy the ‘tiny’ folder into it and restart the Arduino IDE.Delete the extra mac content.

Step 2: Upload the ArduinoISP

  1. Connect your Arduino to your computer.
  2. Open up the ArduinoISP sketch which is with the other example sketches.
  3. Upload it.

Step 3: Connecting the ATtiny2313 to the Arduino

Make the following connections. You need to be sure that you are connecting these to the ATtiny’s actual pins (starting from the top left and counting up counter-clockwise) and not the name of the pin.

Arduino———Attiny2313
  |                   |
13————>19
12————>18
11————>17
10————>1
5v————>20 VCC
GND———>10 GND

Also add an LED with a resistor on the pin (#7) right next to the GND on the ATtiny2313

Step 4: Uploading and Enjoying!

  1. First make sure that you have already uploaded the ArduinoISP to the Arduino.
  2. Select the (ATtiny2313@1MHz) board. When you go to boards you will notice that you will have a lot more options to use. This is because that ‘tiny’ folder that we put in the ‘hardware’ folder gave the Arduino program more board options.
  3. Under ‘programmer’ select ‘Arduino as ISP’.
  4. Open the blink sketch and change the led pin 13 to pin 7.
  5. Click the upload button and pray!

Once you upload it you should have no errors. If you connected the Attiny to the Arduino incorrectly, it’ll bring up the an error and it will say ‘double check connections’.

After upload your LED should start blinking! Congrats! You now know how to program your ATtiny2313.

Troubleshooting:

  • LED does not blink
    Make sure that you have connected the LED to the proper pins.
    Make sure that in the blink sketch you change the 13 to ‘7’.
    Replace the LED and try with another one.
  • Unable to program
    Make sure you have properly download, unzipped, and placed the ‘tiny’ folder.
    Make sure your ‘hardware’ folder is in the correct place.
    Make sure that you have selected ‘Arduino as ISP’ under ‘programmer’.
    Make sure that you have selected the correct board. The correct board is the ‘ATtiny2313@1MGz.

Step 5: Conclusion

I hope this i’ble was able to help you program you chip. You should be able to do this for ATtiny4313. Now I have not actually tried it myself but I will as soon as I get that chip.

Please give it a vote for the microcontroller contest!

and. . .

Don’t forget to favorite and subscribe!

ATtiny2313 Tutorial Introduction

Created on: 23 January 2013

Part 1 of the ATtiny2313 Tutorial

In this first part of the multi-part ATtiny2313A tutorial, we look at what hardware and software is needed to start development work using this 20-pin 8-bit AVR microcontroller from Microchip (formerly from Atmel). This includes the older ATtiny2313 part.

All aspects of development will be covered, including hardware interfacing, software development, internal peripherals, fuse programming and more. An electronic breadboard will be used to build the circuits in this tutorial series.

Prerequisites

In order to follow this series of tutorials on the ATtiny2313, you will need to have some experience in the following fields.

Building Circuits

It is assumed that you have some basic knowledge of electronics and that you can build breadboard circuits. If not, learn about electronics and how to build breadboard circuits in the Start Electronics Now course.

Software Development

To be able to do your own software development, you will need to be able program in the C programming language. If you do not know the C programming language, then it is still possible to follow the tutorials as you will be able to load the C program examples to the microcontroller without having to write your own programs.

Hardware Requirements

Electronic Components

An ATtiny2313 microcontroller in a dual inline package (DIP) is needed (this package is called PDIP in the Atmel literature – Plastic Dual Inline Package). It is recommended to get the ATtiny2313 microcontroller with part number ATTINY2313-20PU.

Other electronic components such as LEDs, resistors, capacitors, etc. are also needed. The required components will be listed in each part of this tutorial as needed in each part.

Breadboard and Power Supply

An electronic breadboard and wire links are needed for building the circuits.

A 5V (five volt) power supply is required for powering the circuits. The 5V from a PC power supply can be used.

Hardware Tools

In order to load a program to the ATtiny2313, a programming device is needed. This device is connected to the USB port of a PC. The header of the programming device is then connected to certain pins of the ATtiny2313 in order to load a program to it.

There are several AVR programming devices to choose from. Some are for programming the AVR microcontroller only, but others have debugging capabilities as well. Some popular programmers are listed below.

AVRISP mkII

The AVRISP mkII is an AVR programmer from Atmel for in-system programming (ISP) of AVR microcontrollers. This programmer does not have any debugging capabilities.

AVR Dragon

The AVR Dragon is an AVR programmer from Atmel for in-system programming, debugging and high-voltage programming (HV programming). HV programming is used to reset certain internal fuse bits of the AVR that ISP programmers can’t reset.

The AVR Dragon is a good choice of programmer as it has more capabilities than a plain ISP programmer.

Be aware that the AVR Dragon is not supplied with any cables. You will need to buy a standard USB cable (not the miniature type) as well as a ribbon cable with a 6-pin (2 by 3 pin) IDC female header on each end. That will be fine for use on this course.

There are two other ribbon cables that can also be plugged into the AVR Dragon. One is for the JTAG connector which is used on some AVR microcontrollers (not the ATtiny2313) and is a 10-pin header (2 by 5 pins). The other ribbon cable is for connecting to the 20-pin (2 by 10) HV programming header and is needed only if doing HV programming.

Home Made Programmer

There are several AVR programmers that can be built at home (for ISP programming only, not for debugging). There is one that works from the PC parallel port and one that works from the PC serial port. Do a search on the Internet to find these.

Another home built AVR programmer that works from a USB port is the open source USBtinyISP. You can build this programmer yourself from scratch or buy a kit and build it.

These home built programmers may need other software to be loaded in order to use them and may not be able to be used directly from within the Atmel AVR Studio software that we will be using in this course.

Software Requirements

Microchip Studio (formerly Atmel Studio version 6.0) is the software development environment and toolchain used in this course. This course was designed and tested using Atmel Studio 6.0 running on Windows 7.

Other versions of Atmel Studio and other versions of Windows should also work.

Getting Set Up

To get the required software installed and to test program the hardware, follow the article Starting AVR 8-bit Development on this website.

This article uses the AVRISP mkII to program a ATtiny2313 microcontroller circuit that flashes an LED on and off. If you are using the AVR Dragon instead, just select the AVR Dragon in the Atmel Studio settings instead of the AVRISP mkII. For other programmers, you will need to follow their specific software requirements and usage instructions.

Once you have followed the above article, you will have the software and hardware installed and tested. You will then be ready to follow the rest of the parts of this tutorial.

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